VLSI Design Environments

VLSI Design Environments

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VLSI Design Environments investigates design alternatives such as object oriented data modelling. The difficulty of automating chip architecture designs is caused by the complexity of the problem. The explosion of design decions make a heuristic approach necessary. PLAYOUT aims at the solution of system problems based on hierarchy, top-down planning, silicon complier presentations, advances in encoding logic synthesis and a microarchitecre and logic optimization system. PLAYOUT supports the physical design from entering the structure of digital systems to the generation of the mask. The concept for autonomous tools with a clear interface to the network description and the simple interface to the graphics is presented. This enables the designer to have a great influence on the configuration of the placement of the schematic diagram. Substantial progress is being made in behavioural and logic synthesis, both of which depend upon specifications.During bottom-up estimation before chip planning (phase I), we estimate the cell area including subcells and internal wiring only. External wiring will not be considered (see above). This area is very close to the smallest possible layouts of aanbsp;...

Title:VLSI Design Environments
Author:George Zobrist
Publisher:CRC Press - 2000-04-17


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