This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards in multiple parallel modes. Moreover, some solutions that can overcome the limitation upon the speedup of parallel architecture by modification to turbo codec are presented here. Compared to the traditional designs, these methods can lead to at most 33% gain in throughput with similar performance and similar cost.The corresponding trellis diagram is given in Fig. ... from 40 to 6144, and these Na#39;s can be summarized as follows: 40+ 8A(ka 0) for k= 0~ 58, 512+16A(ka59) for k= 59Ad 90, 1024+32A(ka91) for k= 91~122, 2048+64x(ka123) for k=123~ 187.
|Title||:||Turbo Decoder Architecture for Beyond-4G Applications|
|Author||:||Cheng-Chi Wong, Hsie-Chia Chang|
|Publisher||:||Springer Science & Business Media - 2013-10-01|