Portland, Oregon, October 13-16, 1987 IEEE Gallium Arsenide Integrated Circuit Symposium ... The switching EFET minimum gate width for the 8 x 8-bit multiplier/ accumulator is 20 urn, while a 10 urn-vide EFET is used in the 4 x 4-bit multiplier. ... The complete 4 x 4-bit and 8 x 8-bit multipliers were extensively simulated with an improved SPICE model, including ... It comprises 8 full-adders, 4 half-adders, logic gates, and drivers, and uses 503 FETs with a minimum switching Table 1anbsp;...
|Title||:||Technical Digest 1987|
|Author||:||IEEE Gallium Arsenide Integrated Circuit Symposium|