Also, a standard 4 bit block size/ 3-level carry look ahead adder [7] is used for the 64 bit fast adder. Using this radix 4 approach, the total delay to compute the product is: 3A for partial product generation/selection (muxes) 36A ... 2.6 Possible Refinements 1) To speed up both the Wallace/Dadda multiplier and the radix 4 hybrid presented, an analysis of a full-adder circuit at the transistor level can be made.

Title | : | Proceedings of the 35th Midwest Symposium on Circuits and Systems |

Author | : | Robert W. Newcomb, Bernard Geller, Mona Elwakkad Zaghloul |

Publisher | : | Piscataway, NJ : Institute of Electrical and Electronics Engineers - 1992 |

Continue