Power-Aware Computer Systems

Power-Aware Computer Systems

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Welcome to the proceedings of the 3rd Power-Aware Computer Systems (PACS 2003) Workshop held in conjunction with the 36th Annual International Symposium on Microarchitecture (MICRO-36). The increase in power and - ergy dissipation in computer systems has begun to limit performance and has also resulted in higher cost and lower reliability. The increase also implies - ducedbatterylifeinportablesystems.Becauseofthemagnitudeoftheproblem, alllevelsofcomputersystems, includingcircuits, architectures, andsoftware, are being employed to address power and energy issues. PACS 2003 was the third workshop in its series to explore power- and energy-awareness at all levels of computer systems and brought together experts from academia and industry. These proceedings include 14 research papers, selected from 43 submissions, spanningawidespectrumofareasinpower-awaresystems.Wehavegrouped the papers into the following categories: (1) compilers, (2) embedded systems, (3) microarchitectures, and (4) cache and memory systems. The ?rst paper on compiler techniques proposes pointer reuse analysis that is biased by runtime information (i.e., the targets of pointers are determined based on the likelihood of their occurrence at runtime) to map accesses to ener- e?cient memory access paths (e.g., avoid tag match). Another paper proposes compiling multiple programs together so that disk accesses across the programs can be synchronized to achieve longer sleep times in disks than if the programs are optimized separat... and Tuning Guide. IBM. (2001) 3. Intel Corporation: (Differences in Optimizing for the Pentium 4 Processor vs. the Pentium III Processor) 4. Intel Corporation: IA- 32 IntelAr Architecture Optimization Reference Manual. (2003) 5. ... Technical report, Compaq: Western Research Laboratory (2001) 19. Yi, J., Lilja, D.: Improvinganbsp;...

Title:Power-Aware Computer Systems
Author:Babak Falsafi, T. N. Vijaykumar
Publisher:Springer Science & Business Media - 2004-12-17


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