Pipelined Analog-to-digital Conversion Using Class-AB Amplifiers

Pipelined Analog-to-digital Conversion Using Class-AB Amplifiers

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In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.2.2 Detailed Circuit Description 2.2.1 MDAC with a Single-Stage Class-AB Amplifier Figure 2.5 shows a half circuit schematic of the MDAC portion of a pipeline stage using the proposed amplifier (the sub-ADC, consisting of conventionalanbsp;...

Title:Pipelined Analog-to-digital Conversion Using Class-AB Amplifiers
Author:Kyung Ryun Kim
Publisher:Stanford University - 2010


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