Master 82496 Cache Controller Write Cycle Table 3-5. Snooping 82496 Cache Controller with Invalidation Request Table. NOTE: The WB/WT# pin will be Writeback (HIGH) for reads or writes to [M] state lines and for writes to [E] state lines.
|Title||:||Pentium Processor User's Manual|
|Publisher||:||McGraw-Hill Companies - 1994-03|