Logic Synthesis and Optimization presents up-to-date research information in a pedagogical form. The authors are recognized as the leading experts on the subject. The focus of the book is on logic minimization and includes such topics as two-level minimization, multi-level minimization, application of binary decision diagrams, delay optimization, asynchronous circuits, spectral method for logic design, field programmable gate array (FPGA) design, EXOR logic synthesis and technology mapping. Examples and illustrations are included so that each contribution can be read independently. Logic Synthesis and Optimization is an indispensable reference for academic researchers as well as professional CAD engineers.1990.  H. Cho, G. Hachtel, M. Nash, and L. Setiono. aBEAT_NP: A Tool for Partitioning Boolean Networks.a Proc. ICCAD88, Nov. ...  S. Dey, F. Berlez, and G. Kedem, aCorolla Based Circuit Partitioning and Resynthesis.a Proc. 27th DACanbsp;...
|Title||:||Logic Synthesis and Optimization|
|Publisher||:||Springer Science & Business Media - 2012-12-06|