Presents modern CMOS logic circuits, fabrication, and layout in a cohesive manner that links the material together with the system-level considerations. * Chapter on Verilog HDL allows for rapid start-up. * Illustrates the top-down design procedure used in modern VLSI chip design with an emphasis on variations in the HDL, logic, circuits and layout.(a) Draw the circuit diagram for a half-adder circuit using the 2-input array in Figure 12.5(a) as a basis. ... (c) Use the 2-input array module in part (b) to model the CPL full- adder. [12.3] Draw the circuits for p( and gt needed for a 4-bit CLA in each of the following CMOS technologies: (a) Static CMOS; (b) Domino CMOS; and (c) TG logic. ... [12.10] Construct a 2 x 2 array multiplier circuit with latching inputs.
|Title||:||Introduction to VLSI Circuits and Systems|
|Author||:||John P. Uyemura|
|Publisher||:||John Wiley & Sons Incorporated - 2002|