This book constitutes the refereed proceedings of the 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006, held in Montpellier, France, in September 2006. The 41 revised full papers and 23 revised poster papers presented together with 4 key notes and 3 industrial abstracts were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on high-level design, power estimation and modeling memory and register files, low-power digital circuits, busses and interconnects, low-power techniques, applications and SoC design, modeling, digital circuits, and reconfigurable and probrammable devices.The U-CBiCMOS buffer driver circuit with pull-up and pull-down MOSFETs is shown in Fig. 3. Fig. ... 5 shows the benchmark circuit of a 4-stage CMOS ( 4SCMOS) inverter based on a normal CMOS/SOI process designed based on the concept of logical effort with fan-out 4 to ... Circuit diagram of U-CBiCMOS buffer driver Fig.
|Title||:||Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation|
|Author||:||Johan Vounckx, Nadine Azemard, Philippe Maurine|
|Publisher||:||Springer Science & Business Media - 2006-09-08|