As the semiconductor technology advances, minimum feature sizes are reduced and clock speeds are increased. Although these changes result in higher performance circuits, their tolerance to errors are reduced, especially when supply voltages are scaled down. Some of the errors are caused by operating environment variations that are introduced during circuit operation and some errors are caused by variations due to manufacturing processes. Failure to account for these variations during the design stage may lead to increased yield loss and decreased reliability in circuits.where g0 = g i and c0 = ci, evaluated at the expansion point, m is the number of RVs involved in Eqn. (4.2), and IWk = Wk ... 4.1.1 Considering Spatial Correlation In this work, we assume that the wire widths are RVs, and that these RVs areanbsp;...
|Title||:||Improving the Robustness of High-speed Clock Distribution Networks|
|Author||:||Wai-Ching Douglas Lam|
|Publisher||:||ProQuest - 2006|