This requires extra D/A and A/D converters with their attendant cost and power increase as well as the 3 dB loss in signal to ... Figure 2 shows the functional block diagram and the actual circuit elements used to demonstrate the feasibility of this concept. ... In the demonstration, the master clock triggers a decision circuit (Sony 1107) at each positive transition of the clock. ... Thus the phases of the master clock and the returning clock could be kept within 120 ps of each other which isanbsp;...
|Title||:||IEEE National Aerospace and Electronics Conference|
|Author||:||IEEE Aerospace and Electronic Systems Society|
|Publisher||:||Institute of Electrical & Electronics Engineers(IEEE) - 1995|