Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.... to that of software. The software life- cycle consists of requirements analysis, design, construction, testing, installation, and maintenance [46]. ... In the development of semantics, the constraints of the language, as specified in the Language Reference Manual, are captured formally. During the ... Semantics validation is performed primarily for two reasons: (1) defect detection, and (2) reliability estimation.

Title | : | Formal Semantics and Proof Techniques for Optimizing VHDL Models |

Author | : | Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey |

Publisher | : | Springer Science & Business Media - 1999 |

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