Each number consists of two fields: 8-bit integer field, and 8-bit fractional field. ... The ALU and register file of the ARP have been inserted in the emulator (85 percent of the FPGA resources is used) and all ... Table 2 shows the resulted speedups when the Verilog model is utilized. ... The reason is that the code loaded into the simulator of the SECOP, is smaller than what is loaded into the simulator in aanbsp;...
|Title||:||Field-Programmable Logic and Applications|
|Author||:||Manfred Glesner, Peter Zipf, Michel Renovell|
|Publisher||:||Springer - 2003-08-02|