FCCM presents recent work on the use of reconfigurable logic as computing elements. The proceedings focuses on topics such as device architecture, system architecture, compilation and programming tools, run time environments, nano technology, and applications.Submodule exploration A library of parameterized FPU submodules was developed aiming high-speed architectures. ... results for different FPU submodules regarding area and clock period for a range of mantissa bit-widths ( exp=8 bits, ... The clock period achievable with minimum pipeline is 64 ns, while the clock for maximum pipelining is 6 ns. ... The designer can specify the floating- point format and the clock period, and the tool produces synthesizable VHDL code of the FPU, anbsp;...
|Author||:||Jeffrey M. Arnold, Kenneth L. Pocek|
|Publisher||:||Institute of Electrical & Electronics Engineers(IEEE) - 2004-01-01|