Maintaining the reliability of data stored in Flash devices and reading it correctly has become a challenge as the demand for higher density is forcing aggressive shrinking of Flash architectures. For all Flash systems, especially latency-constrained NOR Flash, an on-chip error correction code (ECC) is the only viable and robust solution to this problem.This algorithm can be generalized for a t-error correcting code depending upon the required error correction capability for a given block size to maintain ... In the example shown in Figure 4.6, 5 bits of Hamming parity protect a 16 bit data block.
|Title||:||Error Correction Methods for Latency-constrained Flash Memory Systems|
|Publisher||:||ProQuest - 2008|