Embedded SoPC Design with Nios II Processor and Verilog Examples

Embedded SoPC Design with Nios II Processor and Verilog Examples

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Explores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog An SoPC (system on a programmable chip) integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as wella€”allowing us to configure the soft-core processor, create tailored I/O interfaces, and develop specialized hardware accelerators for computation-intensive tasks. Utilizing an Altera FPGA prototyping board and its Nios II soft-core processor, Embedded SoPC Design with Nios II Processor and Verilog Examples takes a qlearn by doingq approach to illustrate the hardware and software design and development process by including realistic projects that can be implemented and tested on the board. Emphasizing hardware design and integration throughout, the book is divided into four major parts: Part I covers HDL and synthesis of custom hardware Part II introduces the Nios II processor and provides an overview of embedded software development Part III demonstrates the design and development of hardware and software of several complex I/O peripherals, including a PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card Part IV provides several case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelbrot set fractal circuit, and an audio synthesizer based on DDFS (direct digital frequency synthesis) methodology While designing and developing an embedded SoPC can be rewarding, the learning can be a long and winding journey. This book shows the trail ahead and guides readers through the initial steps to exploit the full potential of this emerging methodology.When the counter reaches 0, a specific bit is set, the optional interrupt request is asserted, and an optional output pulse can be ... 20 ns) and a 64-bit counter can count up to more than 10, 000 years (i.e., 264 * 20 ns) 0 Hardware options.

Title:Embedded SoPC Design with Nios II Processor and Verilog Examples
Author:Pong P. Chu
Publisher:John Wiley & Sons - 2012-05-14


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