The achieved fault coverages were 95, 6% for the GCD circuit ... Conclusions An analysis has been carried out to formalize the Decision Diagram synthesis from clock-driven multiprocess VHDL descriptions for test generation purposes. ... D. BHATTACHARYA, J. P. HAYES, A Hierarchical Test Generation Metliodology for Digital Circuits, JETTA: Theory a. ... 96-102. 7. R E Bryant, Graph-Based Algoritlims for Boolean Function Manipulation. IEEE Trans, on Comp., 1986, C-3S , 8, 667-690anbsp;...