Digital VLSI Design with Verilog

Digital VLSI Design with Verilog

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This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project. The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70, 000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs. The author includes everything an engineer needs for in-depth understanding of the Verilog language: Syntax, synthesis semantics, simulation and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book. For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. A concluding presentation of special topics includes System Verilog and Verilog-AMS.Therefore, the width ofj must be 3 bits or more; if it were just 2 bits, j would count past 3 to 0, and there never would be a count greater ... One problem with the above code fragment is that it might get stuck in the data and repeatedly jump past the pad bytes. Also, Nkeeper might get filled up with random values whether or not they came from pad bytes. ... Stores 4 nn values. reg[5:0] i; // Indexes into a saved 64-bit SerVect vector. reg[2:0] j // Counts which of 4 assumed nna#39;s we are on.

Title:Digital VLSI Design with Verilog
Author:John Michael Williams
Publisher:Springer - 2014-06-17


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