Using Verilog models and test benches for implementing and explaining fault simulation and test generation algorithms, this book treats the concepts of testing and testability in digital systems, and also covers digital design practices and methodologies.For finding a test vector, the D-Algorithm searches the internal lines of a circuit and sets proper values for fault propagation ... For justifying a 0 on l9, and given that l5 is already set to 1, we have to use the primitive cube 110 that sets l 6 to 1. l6 value of 1 ... to selecting input values for propagations and justifications related to l8 :SA0, we would start with a = b = 1 that activates the fault (see white squares ).

Title | : | Digital System Test and Testable Design |

Author | : | Zainalabedin Navabi |

Publisher | : | Springer Science & Business Media - 2010-12-10 |

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