Digital Computer Arithmetic Datapath Design Using Verilog HDL

Digital Computer Arithmetic Datapath Design Using Verilog HDL

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This text presents basic implementation strategies for arithmetic datapath designs and methodologies utilized in the digital system. The author implements various datapath designs for addition, subtraction, multiplication, and division. Theory is presented to illustrate and explain why certain designs are chosen. Each implementation is discussed in terms of design choices and how particular theory is invoked in the hardware. Along with the theory that emphasizes the design in question, Verilog modules are presented for understanding the basic ideas that accompany each design. Structural models are implemented to guarantee correct synthesis and for incorporation into VLSI schematic-capture programs.The basic idea behind the CSAM is that it is basically doing paper and pencil style multiplication. In other words, each partial product is being added. A 4-bit by 4-bit unsigned CSAM is shown in Figure 4.6. ... A modified full adder (MFA) consists of an AND gate that creates a partial product bit, and a full adder (FA) that addsanbsp;...

Title:Digital Computer Arithmetic Datapath Design Using Verilog HDL
Author:James E. Stine
Publisher:Springer Science & Business Media - 2004


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