Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

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The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.They are not repairable because they do not cause physical damage to the hardware. Dynamic logic and memories are ... A reset or rewriting of the device results in normal device behavior thereafter. An SEU may occur in analog, digital, anbsp;...

Title:Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Author:Manoj Sachdev, Jose Pineda de Gyvez
Publisher:Springer Science & Business Media - 2007-06-04


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