A new configuration for a CMOS under voltage lockout (UVLO) circuit without a band-gap circuit as a reference voltage generator was presented. This new circuit block offers a method to monitor the power supply voltage without consuming a large quiescent current, especially in battery-powered devices, during the sleep mode of operation. The UVLO circuit was fabricated using a 0.5 mum CMOS technology operating at a supply voltage of up to 5V, yielding a low quiescent current of 12muA, an input high threshold voltage of 3.75 V and a hysteresis of 0.55 V. In addition, this dissertation presents a new design procedure for an integrated gate driver circuit to minimize the signal delay in switching converters. This design technique is useful for designing a gate driver circuit using any process technology. In this design, the signal propagation delay is optimized from the input to the output of the driver according to Delay = N Am (1 + HN ); where N is the number of stages and H is the ratio of gate capacitances between the input to output nodes. A new over-current detection/protection circuit based on the hiccup current limit for switching converter is also proposed. This dissertation presents a top-down design of an integrated synchronous hysteretic buck controller. The hysteretic controller with gate driver and over-current protection circuit was fabricated using a 1.5mum CMOS process and tested successfully on the bench. A discussion of the practical limitation of the maximum switching frequency for switching converter is presented.threshold voltage. As can be seen, the UVLO circuit monitors the battery voltage and changes its modes of operation accordingly. 1.4.2 Gate Driver and Over- current protection for Hysteretic Buck Regulator Hysteretic mode control has becomeanbsp;...
|Title||:||Analog Circuit Blocks for Power Management|
|Author||:||Mohammad Rashedul Hoque|
|Publisher||:||ProQuest - 2008|