Abstract: qWe examine empirically the performance of multilevel logic minimization tools for Xilinx Field-Programmable Gate Array (FPGA) technology. The experiments are conducted by using the university tools misII for combinational logic minimization and mustang for state assignment, the Xilinx tools xnf21ca for technology mapping, and apr for automatic placement and routing. We measure the quality of the multilevel logic minimization tools by the number of routed configurable logic blocks (CLBs) in the FPGA realization.1987.  ALDEC, 3525 Old Conejo Rd., Suite 111, Newbury Park, CA 91320, Susie Simulator: Usera#39;s Guide, 1989. ...  S. Devadas, H.-K. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli, aquot;MUSTANG: State assignment of finite stateanbsp;...
|Title||:||An Empirical Study of the Performance of Multilevel Logic Minimization Tools for a Field-programmable Gate Array Technology|
|Author||:||Martine Schlag, Pak K. Chan, Jackson Kong|