A Phase/Frequency Detector (PFD) that has a simple structure and a fast response is presented. This PFD has three signal inputs and no dead zone. The absence of the dead zone reduces an important component of the jitter. An implementation of this PFD in a clock recovery circuit is also presented. A data recovery architecture that uses this fast clock recovery circuit is described. A clock recovery circuit that operates at 1GHz in a 0.6u CMOS N-Well process is discussed.A Phase/Frequency Detector (PFD) that has a simple structure and a fast response is presented.
|Title||:||A High Speed Data Recovery Circuit with Lead/lag Phase Detection|
|Author||:||Mezyad M. Amourah|